1. Field of the Invention
The present application relates to a method and apparatus for measuring and mapping strain on an integrated circuit die, and more particularly to using strain gauges that correlate resistance changes to strain at the die level.
2. Background Information
A significant failure mode in integrated circuit chips stems from strains generated during the fabrication of the chip and by environmental conditions including internally generated heat. The strains may damage the chips. Measuring strain at the chip level during chip fabrication may suggest changes to the chip fabrication processes to reduce the strain and improve the production yield.
Use of strain gauges is well known in the art for measuring strains on surfaces. They are used by fixing or bonding the strain gauge to the article, and using the strain gauge as one or more legs in a Wheatstone Bridge or equivalent circuit. As stresses on the article cause it to distort or change its physical shape, the attached strain gauge changes its physical dimensions and thus its resistance. The bridge detector senses the change in resistance. The resistance change of the strain gauge is correlated to strains in the surface. These prior art strain gauges are usually made of metal foils, but are not suitable for measuring strains at the integrated circuit die level.
Herein chip, integrated circuit and die may be used interchangeably and define the “chip” with respect to the IC package containing the chip.
Others have developed Moire interferometry that can detect and measure distortion or warpage of an integrated circuit package, but such techniques cannot be used to measure the chip itself, since it is hidden within the package.
At the integrated circuit die level, others have suggested strain measuring devices using piezo-electric material where an electrical output is generated by physical strains on a crystal. Such strain gauges are unwieldy and difficult to use on a die.
Still others have used standard type diffusions (that are used to fabricate electronic circuits on a chip) to form elements to measure strain on a chip. However, the use of diffusions typically include forming pn junctions. Such junctions may form complex circuitry from intrinsic electronic components (diodes, transistors, capacitors) that may adversely affect strain measurements. Using diffusions also entails construction as complex as fabricating a full integrated circuit, e.g. a circuit that might be used in a digital processor or the like. Another limitation of such semiconductor strain gauges is that they cannot be easily arranged to measure vertical strain of an integrated circuit. Vertical here meaning the direction of depth into a chip as compared to the x-y surface of the chip.
The known prior art present limitations where traditional strain gauges are simply not suitable for application to integrated circuit dies or they are more complex to fabricate and use.
It would advantageous to provide strain mapping over the top and lower surfaces of a chip during fabrication and in a specific application environment.